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LSI/CSI
UL
(R)
LS7260 LS7262
(631) 271-0400 FAX (631) 271-0405
November 1997
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
BRUSHLESS DC MOTOR COMMUTATOR/CONTROLLER
FEATURES: * Direct drive of P-Channel and N-Channel FETs (LS7260) * Direct drive of PNP and NPN transistors (LS7262) * Six outputs drive power switching bridge directly * Open or closed loop motor speed control. * +5V to +28V operation (Vss - VDD). * Externally selectable input to output code for 60, * * * * * * *
120, 240, or 300 electrical sensor spacing. Three or four phase operation Analog Speed control Direction control Output Enable control Positive Static Braking Overcurrent Sensing LS7260, LS7262 (DIP); LS7260-S, LS7262-S (SOIC) LS7260-TS, LS7262-TS (TSSOP) - See Connection Diag.
CONNECTION DIAGRAM - TOP VIEW
CS1 OUT 1 OUT 2 OUT 3 COMMON OUT 4 OUT 5 OUT 6 BRAKE ENABLE
1
20 19 18 17 16 15 14 13 12 11
CS2 FWD/REV V DD (-V) S3 S2 S1 OSCILLATOR V TRIP OVERCURRENT SENSE V SS (+V)
LSI
2 3 4 5 6 7 8 9 10
DESCRIPTION:
The LS7260/LS7262 are monolithic, MOS integrated circuits designed to generate the signals necessary to control a three phase or four phase brushless DC motor. They are the basic building blocks of a brushless DC motor controller. The circuits respond to changes at the SENSE inputs, originating at the motor position sensors, to provide electronic commutation of the motor windings. Pulse Width Modulation of outputs for motor speed control is accomplished through either the ENABLE input or through the Analog input (VTRIP) in conjunction with the OSCILLATOR input. Overcurrent circuitry is provided to protect the windings, associated drivers and power supply. The overcurrent circuitry causes the external output drivers to switch off immediately upon sensing the overcurrent condition and on again only when the overcurrent condition disappears and the positive edge of either the ENABLE input or the sawtooth OSCILLATOR occurs. This limits the overcurrent sense cycling to the chopping rate of the ENABLE input or the sawtooth OSCILLATOR. A positive braking feature is provided to effect rapid deceleration. While the LS7262 is designed for driving NPN and PNP transistors (See Fig. 2), the LS7260 is designed to drive both NMOS and PMOS Power FETs and develops a full 12V drive for both the N-Channel and P-Channel devices (See Fig. 1) when using a 12V power supply.
INPUT/OUTPUT DESCRIPTION: COMMUTATION SELECTS (Pins 1, 20) These inputs are used to select the proper sequence of outputs based on the electrical separation of the motor position sensors. See Table 3. Note that in all cases the external output drivers are disabled for invalid SENSE input codes. Internal pull down resistors are provided at Pins 1 and 20 causing a logic zero when these pins are left open. FORWARD/REVERSE (Pin 19) This input is used to select the proper sequence of Outputs for the desired direction of rotation for the Motor (See Table 3). An internal pull-up resistor holds the input high when left open. SENSE INPUTS (Pins 15, 16, 17) These inputs provide control of the output commutation sequence as shown in Table 3. S1, S2, S3 originate in the position sensors of the motor and must sequence in cycle code order. Hall Switch pull-up resistors are provided at Pins 15, 16 and 17. The positive supply of the Hall devices should be common to the chip Vss. BRAKE (Pin 9) For the LS7262, a high level at this input unconditionally turns OFF Outputs 1, 2 and 3 and turns ON Outputs 4, 5 and 6 (See Fig. 2). For the LS7260, a high level at this input turns ON Outputs 1, 2 and 3 and Outputs 4, 5 and 6 (See Fig. 1). In both cases, transistors Q101, Q102 and Q103 cut off and transistors Q104, Q105 and Q106 turn on, shorting the windings together, The BRAKE has priority over all other inputs.
7260-041100-1
BRAKE (Pin 9) (Cont'd) An internal pull-down resistor holds the input low when left open. (Center- tapped motor configuration requires a power supply disconnect transistor controlled by the BRAKE signal - See Figure 2A). ENABLE (Pin 10) A high level at this input permits the output to sequence as in Table 3, while a low disables all external output drivers. An internal pull-up resistor holds the input high when left open. Positive edges at this input will reset the overcurrent flip-flop. OVERCURRENT SENSE (Pin 12) This input provides the user a way of protecting the motor winding, drivers and power supply from an overload condition. The user provides a fractional-ohm resistor between the negative supply and the common emitters of the NPN drivers or common sources of N-Channel FET drivers. This point is connected to one end of a potentiometer (e.g. 100K ohms), the other end of which is connected to the positive supply. The wiper pickoff is adjusted so that all outputs are disabled for currents greater than the limit. The action of the input is to disable all external output drivers. When BRAKE exists, OVERCURRENT SENSE will be overridden. The overcurrent circuitry latches the overcurrent condition. The latch may be reset by the positive edge of either the sawtooth OSCILLATOR or the ENABLE input. When using the ENABLE input as a chopped input, the OSC input should be held at VSS. When the ENABLE input is held high, the OSCmust be used to reset the overcurrent latch. VTRIP (Pin 13) This input is used in conjunction with the sawtooth OSC input. When the voltage level applied to VTRIP is more negative than the waveform at the OSC input, the Outputs will be enabled as shown in Table 3. When VTRIP is more positive than the sawtooth OSCILLATOR waveform the external output drivers are disabled.
MAXIMUM RATINGS: PARAMETER Storage Temperature Operating Temperature Voltage (any pin to Vss)
The sawtooth waveform at the OSC input typically varies from .4 Vss to Vss-2V. The purpose of the VTRIP input in conjunction with the OSCILLATOR is to provide variable speed adjustment for the motor by means of PWM. OSCILLATOR (Pin 14) An R and C connected to this input (See Figure 6) provide the timing components for a sawtooth OSCILLATOR. The signal generated is used in conjunction with VTRIP to provide PWM for variable speed applications and to reset the overcurrent condition. OUTPUTS 1, 2, 3 (Pins 2, 3, 4) For the LS7262, these open drain Outputs are enabled as shown in Table 2 and provide base current to PNP transistors or gate drive to P-Channel FET drivers when COMMON is floating. If COMMON is held at Vss, these Outputs can provide drive to NPN transistors or N-Channel FET drivers. For the LS7260, these Outputs provide drive to P-Channel FET drivers if COMMON is held at VSS. OUTPUTS 4, 5, 6 (Pins 6, 7, 8) These open drain Outputs are enabled as in Table 2 and provide base current to NPN transistors or gate drive to N-Channel FET drivers. COMMON (Pin 5) The COMMON may be connected to Vss when using a center-tapped motor configuration or when using all NPN or N-Channel drivers. For the LS7260, the COMMON is tied to VSS. Vss (Pin 11) Supply voltage positive terminal. VDD (Pin 18) Supply voltage negative terminal (ground).
SYMBOL TSTG TA TA (1) VMAX
VALUE -65 to +150 -25 to +85 -40 to +125 -30 to +.5
UNIT C C C V
(1) Available on special order. Contact factory for details. DC ELECTRICAL CHARACTERISTICS: (All Voltages Referenced to VDD, TA = 25C unless otherwise specified) SYMBOL MIN Supply Voltage VSS 5 Supply Current (Outputs not loaded) IDD Input Specifications: BRAKE, ENABLE, CS1, CS2 S1, S2, S3, FWD/REV Voltage (Logic "1") (Logic "0") OVERCURRENT SENSE (See Note) Threshold Voltage
TYP 4.5
MAX 28 6
UNIT V mA
RIN VIH VIL VTH
VSS-1.5 0 (VSS/2)-.25
150 -
VSS VSS-4.0 (VSS/2)+.25
K V V V
7260-111297-2
Oscillator: Frequency Range External Resistor Range
Fosc Rosc
0 22
1/RC -
100 1000
kHz k
NOTE: Theoretical switching point of the OVERCURRENT SENSE input is one half of the power supply determined by an internal bias network in manufacturing. Tolerances cause the switching point to vary plus or minus .25V. After manufacture, the switching point remains fixed within 10mV over time and temperature. The input switching sensivity is a maximum of 50mV. There is no hysteresis on the OVERCURRENT SENSE input.
TYPICAL CIRCUIT OPERATION: The oscillator is used for motor speed control as explained under VTRIP. Both upper and lower motor drive transistors are pulse width modulated (See Fig. 1 or 2) during speed control. For the LS7262, the outputs turn on in pairs (See Table 3). For example (See dotted line, Fig. 2): Q8 and Q4 are on, thus enabling a path from the positive supply through the emitter-base junction of Q101, Q8, Q4, R5, the base emitter junction of Q105 and the fractional-ohm resistor to ground. The current in the above described path is determined by the power supply voltage, the voltage drops across the base-emitter junctions of Q101 and Q105 (1.4V for single transistor or 2.8V for Darlington pairs), the impedance of Q8 and Q4 and the value of R5. Table 1 provides the recommended value for R5. R4 and R6 are the same value. TABLE 1 OUTPUT CURRENT LIMITING RESISTOR SELECTION TABLE POWER OUTPUT CURRENT SUPPLY (VOLTS) 20 15 10 7.5 5 2.5 mA 6 9 12 15 18 21 24 28 ** ** ** ** ** ** ** ** .43 .86 .20 .33 .62 .91 1.5 .36 .56 .91 1.3 2.2 * .75 1.2 1.6 2.7 * * 1.5 2.0 3.3 * * 1.8 2.3 3.6 * * * 2.7 4.3 .24 2.2 3.3 4.3 Resistance 5.1 (k) 6.2 7.5 9.1
For the LS7260, (See Fig. 1) the external drivers also turn on in pairs. Internal operation is somewhat different than the LS7262. For example, external transistors Q101 and Q105 will turn on when internal transistor Q8 turns off and Q4 turns on enabling full power supply drive on Q101 and Q105. Since Pin 5 is tied to VSS, the gate of Pchannel Driver Q101 is brought to ground by R1 and the Gate of N-Channel driver Q105 is brought to VSS by Q4. Other external output pairs turn on similarly and the commutation sequence is identical to that of the LS7262 (Table 3). Table 2 indicates the minimum value of R1 (=R2=R3=R4=R5=R6) needed as a function of output drive voltage for Fig. 1.
TABLE 2 For Power Supply 5V-28V R1 (k ohms) 10 4.0 1.5 Output Voltage Vss -0.5 Vss -1.0 Vss -2.0
*causes excessive power dissipation **exceeds max current possible for this voltage
TABLE 3. OUTPUT COMMUTATION SEQUENCE FOR THREE PHASE OPERATION CS1 CS2 0 0 ELECTRICAL SEPARATION (-60-) SENSE INPUTS S1 S2 S3 000 100 110 111 * See Figures 1 and 2. 011 For the LS7260, 001 Outputs O1,O2,O3 are the logical inversions of 010 the corresponding Out101 puts of the LS7262. SEQUENCE SELECT CS1 CS2 0 1 (-120-) S1 S2 S3 001 101 100 110 010 011 000 111 CS1 CS2 CS1 CS2 1 0 1 1 (-240-) (-300-) S1 S2 S3 S1 S2 S3 010 011 110 111 100 110 101 100 001 000 011 001 000 111 010 101 FWD/REV=1 OUTPUTS * DRIVERS * ENABLED A B C O1, O5 + Off O3, O5 Off + O3, O4 Off + O2, O4 + Off O2, O6 Off + O1, O6 + Off ALL DISABLED ALL DISABLED FWD/REV=0 OUTPUTS * ENABLED O2, O4 O2, O6 O1, O6 O1, O5 O3, O5 O3, O4 DRIVERS * A B C + Off Off + + Off + Off Off + Off +
ALL DISABLED ALL DISABLED
The OVERCURRENT input (BRAKE low) enables external output drivers in normal sequence when more negative than Vss/2 and disables all external output drivers when more positive than Vss/2. The OVERCURRENT is sensed continuously, and sets a flip flop which is reset by the rising edge of the ENABLE input or the sawtooth OSCILLATOR. (See description under OVERCURRENT SENSE.) The VTRIP Input (BRAKE low) enables the outputs in normal sequence when more negative than the OSC input and disables all outputs when more positive than the OSC input. The VTRIP input may be disabled by connecting it to VDD and the OSC input to VSS. (See description under VTRIP)
7260-111397-3
Vss P
O1
P
Q101 Q102
P
Q103
2 3
O2
R1 R2
O3
R3
4
Q8 Q6
Q7
L3 5 A L1 B L2 C
Output Encoder
Q5 Q4 Q3
M O T O R
8
O5
O6
7 Vss 12 6
O4
N
Q104
N
Q105
N
Q106
R4 TO OVERCURRENT ADJUSTMENT
R5
R6
Fractional Ohm Resistor
FIGURE 1. LS7260 THREE PHASE OUTPUT DRIVER CIRCUITRY
Vss Direction of Current Flow
11 R1 BRAKE 2 3
O1 O2
R2 Q101 Q102
R3 Q103
4 Q8 Q6
O3 M O T O R
Output Encoder
Q7
L3 5 A R6 8
O5 O6
L1
B
L2
C
Q5
Q4
Q3
R5 R4 Q104 R7
7
Vss
6
O4
Q105 R8 R9
Q106
12
TO OVERCURRENT ADJUSTMENT
Fractional Ohm Resistor
FIGURE 2. LS7262 THREE PHASE OUTPUT DRIVER CIRCUITRY
7260-100897-4
O4
6
BRAKE BRAKE 9 INPUT O5 LS7262 7
FIGURE 2A. SINGLE-ENDED DRIVER CIRCUIT This configuration requires only one base current limiting resistor connected from the COMMON pin to Vss.
MOTOR SUPPLY
COMMON O6
5
Vss
8
19 FORWARD IN914
F/R LS7260 or LS7262
REVERSE IN914 Inputs from SG1731 or UC1637
10 ENABLE
2.2K
FIGURE 3. PRECISION CONTROL BRUSHLESS DC MOTOR DRIVE For controlled acceleration and deceleration of motors in the forward or reverse directions, a motor control pulse width modulator circuit such as the SG1731 or UC1637 can be interfaced with the LS7260 or LS7262. The logical OR gate made up of the resistor-diode network permits the LS7260 or LS7262 to be enabled when either the forward or reverse input is high. By applying the forward input directly to Pin 19, the motor can only operate in the forward direction when the forward input is high and only in the reverse direction when the reverse input is high. Motor direction is determined by relative pulse widths of the forward and reverse inputs while acceleration or deceleration is determined by variations of these widths.
TABLE 4. OUTPUT COMMUTATION SEQUENCE FOR FOUR PHASE OPERATION CS1=CS2=0 OUTPUTS ENABLED
S1 0 1 1 0 S2,S3 0 0 1 1 FWD/REV = 1 O1 O3 O4 O6 FWD/REV = 0 O4 O6 O1 O3
For four phase commutation (See Fig. 4), the COMMUTATION SELECT inputs must both be tied low. The S1 input is driven from one motor position sensor while the S2 and S3 inputs are connected together and driven by the second position sensor. The COMMON input must be
7260-110697-5
connected to Vss. The sensors have an electrical separation of 90. Figure 4A indicates the use of Bipolar Transistors. Figure 4B indicates the use of FETs. In both cases, the LS7262 is used.
FIGURE 4. FOUR PHASE OUTPUT DRIVER CIRCUITRY
FIGURE 4A
MOTOR SUPPLY
FIGURE 4B
MOTOR SUPPLY
5 COMMON 9 BRAKE INPUT L1 2 Vss
COMMON BRAKE O1
5 9 2
Vss
L1
O1
L2
L2 4
O3
4
O3
LS7262
L3 6 O4 BRAKE
LS7262
L3 BRAKE O4 6
L4 8 O6
L4 8 O6
12 OVERCURRENT SENSE Vss
OVERCURRENT SENSE
12
Vss
Vss
FROM MOTOR POSITION SENSOR Vss
R1 15 S1
FIGURE 5 CLOSED-LOOP SPEED CONTROLLER
A closed loop system can be configured by differentiating one of the motor position sense inputs and integrating only the negative pulses to form a DC voltage that is applied to the inverting input of an op-amp. The non-inverting input voltage is adjusted with a potentiometer until the resultant voltage at VTRIP causes the motor to run at desired speed. The R2-C1 differentiator, the R3-D1 negative pulse transmitter and the R4-C2 integrator form a frequency to voltage converter. An increase in motor speed above the desired speed causes VTRIP to increase which lowers the PWM and the resultant motor speed. A decrease in speed lowers VTRIP and raises the PWM and the resultant motor speed. For proper operation, both R5 and R6 should be greater than R4, and R4 in turn should be greater than both R2 and R3. Also, the R4-C2 time constant should be greater than the R2-C1 time constant. C3 may be added across R6 for additional VTRIP smoothing.
R3 D1
R2 C1 C3 R5 R6 13 V TRIP
R4
LS7260 or LS7262
C2
+
Vss
Vss
C4 14 OSCILLATOR
R7
R8
The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
7260-082697-6
CS1 CS2
1 20
COMMUTATION SEQUENCE SELECT LOGIC
4 COMMON 5 8
+V INPUT DECODER FWD/REV 19 6
2 O1
OUTPUT DRIVERS
3 O2 4 O3 6 O4
S1 15 S2 16 S3 17 BRAKE 9 +V OUTPUT ENCODER
7 O5 8 O6
R ENABLE 10
POSITIVE EDGE DETECTOR
R
Q
R OVERCURRENT 12 SENSE V TRIP +V .001F 14 33K 13
+
-
S
POSITIVE EDGE DETECTOR +
+V SAWTOOTH OSCILLATOR GND
11 VSS 18 VDD
NOTE: With indicated components, oscillator frequency is approximately 30KHz.
FIGURE 6. LS7260 AND LS7262 BLOCK DIAGRAM
AM

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